The present invention is related to a method of fabricating a core laminate Printed Circuit Board.
Requirements for higher reliability, better performance and lower system cost are the driving forces behind the current development of new high density packaging (HDP) technologies and miniaturized electronic systems. Different technological approaches are available to achieve high density interconnection structures. These are generally based on improvements on existing technology, such as printed circuit board, co-fired ceramic or thin film technology. Each of these technologies has their specific merits and drawbacks.
When it comes to achieving the highest interconnection density with the best electrical performance, the multilayer thin film technology is now generally accepted as the highest performance technology. A very dense interconnection pattern can be realised using only two fine-line routing layers. These thin film structures are generally produced on silicon, glass, ceramic or even metallic substrates that have only a function as carrier for the thin film layers. After assembly of the die on such a substrate, the substrate itself needs to be packaged. This is an important disadvantage, compared to laminate or ceramic high density interconnect substrates. These can be considered as ball-grid-array xe2x80x9cinterposerxe2x80x9d substrates, therefore not requiring any additional packaging, except for overmoulding and solder-ball attachment.
Printed Circuit Boards fabricated by laminate technology use thick metal lines (e.g., 20 to 60 micron thick conductors) as interconnect lines and thick dielectric layers (e.g., 25 to 100 micron) as interlayer isolators. Thin film technology on the other hand uses thin metal lines (e.g., 2 to 5 micron thick conductors) and thin dielectric layers (e.g., 5 to 10 micron thick MCM-D dielectrics). Feature sizes of lines and spaces in this technology can easily go down to 20 or even 10 xcexcm. Therefore, the metal and dielectric thicknesses can be an order of magnitude larger in PCB technology than in thin film technology. The laminate should thus also be sufficiently planar on a local scale in order to allow for a reliable coating with thin film layers. This requires planarisation.
Previous techniques at planarization have not been adequate. For example, resins have been applied to the PCB surface in order to planarize the surface; however, these efforts have proven complicated and at time ineffective. Specifically, prior efforts have attempted to drop the resinous material onto the center of the surface of the PCB while the PCB is spinning. Due to centrifugal force, the resinous material is spread on the upper surface of the PCB. This method, however, is complicated in its processing. Moreover, the resinous material on the upper surface of the PCB may not be entirely planar.
An aim of the invention is to manufacture a core laminate printed circuit board structure with highly planar external surfaces.
Another aim of the invention is to provide a printed circuit board that has a suitable base substrate for a thin film multilayer build-up structure.
Still another aim of the invention is to provide a printed circuit board that has electrical connections between the thin film top layers and the printed circuit board style core layers.
The present invention is related to a method of fabricating a core laminate printed circuit board structure with highly planar external surfaces. The proposed method comprises the use of a pre-formed flat material adhered to a printed circuit board (PCB). In one embodiment, the pre-formed flat material is in the form of a sheet and includes at least two types of sub-materials that abut one another. The first sub-material is a resinous or viscous substance that has the ability to flow during lamination. The second sub-material is, in one embodiment, a sacrificial layer and only serves as a carrier for the first sub-material. The second sub-material is not a resinous or viscous substance and does not have the ability to flow during lamination. In one embodiment, the pre-formed flat material is a thin Resin Coated Copper (RCC) foil. The RCC foil is formed in sheets with a first sub-material of resin (or other material which flows during lamination) and with a second sub-material of copper (or other conductor).
In one embodiment, the method includes laying a sheet of the pre-formed flat material on the PCB, with the first sub-material coming into contact with the upper surface of the PCB. The upper surface of the PCB may not be planar, due to crevices, vias, etc. The pre-formed flat sheet sits on the upper surface of the PCB with the first sub-material not filling the crevices, vias, etc. For at least for a part of the time during lamination, uniform pressure is applied to the pre-formed flat sheet which covers the upper surface of the PCB. In one embodiment, the uniform pressure is applied using iron plates during lamination. Therefore, the resinous material of the first sub-material flows to fill the crevices, vias, etc. of the upper surface of the PCB. Moreover, due to the uniform pressure on the pre-formed flat sheet, the resinous first sub-material is planarized.
After lamination, the second sub-material may be removed completely or removed partially. In a preferred embodiment, wherein the material is an RCC foil, the second sub-material (e.g., copper layer), covering the RCC foil, serves as a sacrificial layer and can be removed, such as by etching, thereby leaving an entirely planar or substantially planar epoxy surface. In an alternate embodiment, the second sub-material (e.g., copper layer) can also be patterned as an interconnect layer. In addition, in one embodiment, more than one RCC foil can be subsequently applied.
These and other advantages of the invention will be more apparent to one of the ordinary skill in the art after reading the detailed description section with references to the accompanying drawings.